| US 7,467,289 B1 | ||
| Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited | ||
| Lincoln G. Garlick, Santa Clara, Calif. (US); Vikramjeet Singh, Fremont, Calif. (US); David W. Nuechterlein, Longmont, Colo. (US); Shail Dave, San Jose, Calif. (US); Jeffrey M. Smith, Union City, Calif. (US); Paolo E. Sabella, San Francisco, Calif. (US); and Dennis K. Ma, San Jose, Calif. (US) | ||
| Assigned to NVIDIA Corporation, Santa Clara, Calif. (US) | ||
| Filed on Oct. 27, 2006, as Appl. No. 11/553,913. | ||
| Int. Cl. G06F 11/30 (2006.01) | ||
| U.S. Cl. 712—228 [714/47] | 18 Claims |
| 1. A method of freezing at least a portion of processing within a processor supporting multiple independent resources from
a common pipeline, the method comprising:
determining assertion of at least one bit of a freeze register within the processor;
determining, based on the at least one bit, a level of freeze;
inhibiting processing of at least one common process within the processor based on the level of freeze by inhibiting further
context switching of resources within the processor; and
asserting an acknowledge indication.
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