| US 7,467,277 B2 | ||
| Memory controller operating in a system with a variable system clock | ||
| Melissa Ann Barnum, Kasson, Minn. (US); Mark David Bellows, Rochester, Minn. (US); Paul Allen Ganfield, Rochester, Minn. (US); Lonny Lambrecht, Byron, Minn. (US); and Tolga Ozguner, Rochester, Minn. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Feb. 07, 2006, as Appl. No. 11/348,879. | ||
| Prior Publication US 2007/0183192 A1, Aug. 09, 2007 | ||
| Int. Cl. G06F 13/14 (2006.01) | ||
| U.S. Cl. 711—167 [711/158; 713/322; 713/600] | 9 Claims |
| 1. A method for transferring read data from memory driven by a constant memory clock to a processor driven by a variable processor
clock by means of an asynchronous read buffer configured to receive read data from memory driven by the memory clock and send
read data to the processor driven by the processor clock, comprising:
receiving a slow mode request from a clock controller to lower a frequency of the processor clock;
in response to receiving the slow mode request, stalling processing of read commands until all pending read commands are completed;
determining a rate for issuing read commands; and
after the pending read commands are completed, issuing read commands at the determined rate, wherein the determined rate is
selected to prevent overflow of the read buffer.
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