| US 7,467,256 B2 | ||
| Processor having content addressable memory for block-based queue structures | ||
| Sanjeev Jain, Shrewsbury, Mass. (US); Gilbert M. Wolrich, Framingham, Mass. (US); and Debra Bernstein, Sudbury, Mass. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 28, 2004, as Appl. No. 11/27,601. | ||
| Prior Publication US 2006/0143373 A1, Jun. 29, 2006 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—108 [711/154; 711/169; 365/49.1; 710/39] | 16 Claims |
| 1. A processor system comprising:
a content addressable memory (CAM) comprising:
a plurality of CAM entries each comprising:
a tag field;
first and second pointer fields to contain pointers to define a link list of information in the tag field;
a command store field to store at least a portion of a command; and
a data store field to store data associated with the command,
wherein at least some of the data associated with the command is configured to have a first portion stored in the data store
field of a first one of the plurality of CAM entries and a second portion stored in the data store field of a second one of
the plurality of CAM entries,
wherein the data store field of the first one of the plurality of CAM entries and the data store field of the second one of
the plurality of CAM entries are configured to store a queue descriptor.
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