US 7,466,922 B2
Flexible control and status architecture for optical modules
Jay J. Pierce, Melbourne, Fla. (US); Darrel Kanagy, Melbourne, Fla. (US); David Schneider, Melbourne, Fla. (US); and Christopher A. Zuhlke, Indian Harbour Beach, Fla. (US)
Assigned to JDS Uniphase Corporation, Milpitas, Calif. (US)
Filed on Jun. 27, 2005, as Appl. No. 11/167,410.
Claims priority of provisional application 60/583587, filed on Jun. 28, 2004.
Prior Publication US 2005/0286902 A1, Dec. 29, 2005
Int. Cl. H04B 10/04 (2006.01); H04B 10/06 (2006.01)
U.S. Cl. 398—135  [398/182; 398/202] 18 Claims
OG exemplary drawing
 
1. An optoelectronic module for transmitting or receiving optical signals through a fiber-optic link, the module comprising:
an electrical I/O port for connecting the module to an external host device, comprising first connection means for providing discrete electrical connections therebetween for a plurality of digital control and status (C&S) signals, said plurality of digital C&S signals comprising digital control signals and digital status signals;
an optical port for connecting to the fiber-optic link;
functional hardware responsive to the digital control signals, comprising:
a) one of electro-optic generating means for generating an output optical signal, and opto-electronic receiving means for receiving an input optical signal and for converting thereof into a received electrical signal; and,
b) sensing means for providing status information and for generating the digital status signals;
processing means for processing the plurality of digital control and status signals, the processing means comprising a processor and an FPGA;
electrical circuitry for establishing communication paths between the electrical I/O port of the module, the processing means and the functional hardware;
wherein the FPGA is disposed in the communication paths between said first connection means on one side, and the functional hardware and the processor on the other side, and programmed with an instruction set for routing each of the digital control and status signals between the first connection means and the processor, and the first connection means and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions.