US 7,466,751 B2
System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
Oscar E. Azazzi, Irvine, Calif. (US); David Kruse, Newport Beach, Calif. (US); Arthur Abnous, Irvine, Calif. (US); and Mehdi Hatamian, Mission Viejo, Calif. (US)
Assigned to Broadcom Corporation, Irvine, Calif. (US)
Filed on Aug. 16, 2005, as Appl. No. 11/204,534.
Application 11/204534 is a continuation of application No. 09/858760, filed on May 15, 2001, granted, now 6,947,482.
Application 09/858760 is a continuation of application No. 09/370354, filed on Aug. 09, 1999, granted, now 6,249,544.
Claims priority of provisional application 60/130616, filed on Apr. 22, 1999.
Claims priority of provisional application 60/116946, filed on Jan. 20, 1999.
Claims priority of provisional application 60/108319, filed on Nov. 13, 1998.
Prior Publication US 2006/0034402 A1, Feb. 16, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. H03H 7/30 (2006.01)
U.S. Cl. 375—233  [375/350] 12 Claims
OG exemplary drawing
 
1. A receiver for demodulating an analog signal transmitted by a remote transmitter over a transmission channel, the analog signal including a first ISI component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel, the receiver comprising:
an analog front end, including an analog-to-digital converter, the analog front end receiving and converting the analog signal to a first digital signal;
an equalizer block coupled to the analog front end to receive the first digital signal, the equalizer block compensating the first ISI component in the first digital signal and outputting a second digital signal, the equalizer block comprising an ISI compensation filter having an impulse response substantially inverse of the impulse response of the pulse shaping filter of the remote transmitter, the equalizer block further comprising an adaptive gain stage; and
a decision feedback sequence estimation block, including an ISI compensation circuit, the ISI compensation circuit receiving the second digital signal outputted by the equalizer block and compensating the second ISI component in the second digital signal.