| US 7,466,508 B2 | ||
| Impedance-matched write circuit with shunted matching resistor | ||
| Hao Fang, Savage, Minn. (US); and Cameron C. Rabe, Inver Grove Heights, Minn. (US) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Feb. 11, 2004, as Appl. No. 10/776,701. | ||
| Prior Publication US 2005/0174668 A1, Aug. 11, 2005 | ||
| Int. Cl. G11B 5/02 (2006.01) | ||
| U.S. Cl. 360—68 | 21 Claims |
| 1. An impedance matched write circuit, comprising:
an interconnect for connecting to a write head;
at least one resistor between a control voltage and said interconnect for impedance matching to said inter connect;
a transistor circuit connected across said at least one resistor to shunt at least a portion of the current that would otherwise
pass through said at least one resistor during an over shoot mode.
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