| US 7,466,140 B2 | ||
| Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus | ||
| Kiyotaka Ichiyama, Tokyo (Japan); and Masahiro Ishida, Tokyo (Japan) | ||
| Assigned to Advantest Corporation, Tokyo (Japan) | ||
| Filed on Dec. 25, 2006, as Appl. No. 11/616,009. | ||
| Prior Publication US 2008/0150603 A1, Jun. 26, 2008 | ||
| Int. Cl. G01R 31/08 (2006.01) | ||
| U.S. Cl. 324—537 [375/235; 375/344; 375/346; 375/224; 375/226; 327/291; 331/2] | 16 Claims |
| 1. A signal generation circuit for generating an output signal including jitter injected thereto, the signal generation circuit
comprising:
a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from
each other;
a carrier output section that outputs a carrier signal having a frequency positioned in substantially the middle between the
frequencies of the first and second jitter signals; and
an adding section that adds together the first jitter signal, second jitter signal and carrier signal so as to generate the
output signal.
|