| US 7,465,639 B1 | ||
| Method for fabricating an SOI device | ||
| Mario M. Pelella, Mountain View, Calif. (US); Richard K. Klein, Mountain View, Calif. (US); and James Werking, Danbury, Conn. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on May 20, 2005, as Appl. No. 11/133,969. | ||
| Int. Cl. H01L 21/20 (2006.01) | ||
| U.S. Cl. 438—384 | 19 Claims |
| 1. A method for fabricating a silicon on insulator (SOI) device comprising a silicon substrate, a buried insulator layer overlying
the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the
steps of:
forming a dielectric isolation region extending through the monocrystalline silicon layer;
etching an opening extending through the dielectric isolation region and the buried insulator region to expose a portion of
the silicon substrate;
doping a portion of the silicon substrate exposed through the opening with a conductivity determining dopant of a first conductivity
type;
doping a portion of the monocrystalline silicon layer with impurity dopants of a second conductivity type to form a first
plate of a capacitor;
forming an insulator layer overlying the portion of the monocrystalline silicon layer;
forming a conductive electrode overlying the insulator layer to form a second plate of the capacitor;
coupling a first bus to the first plate of the capacitor and to the doped portion of the silicon substrate; and
coupling a second bus to the second plate of the capacitor.
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