| US 7,465,623 B2 | ||
| Methods for fabricating a semiconductor device on an SOI substrate | ||
| Mario M. Pelella, Mountain View, Calif. (US); and Darin A. Chan, Campbell, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Aug. 28, 2006, as Appl. No. 11/467,634. | ||
| Prior Publication US 2008/0124884 A1, May 29, 2008 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—221 [438/199; 438/218; 438/222; 438/232; 438/403; 438/424; 257/E21.642] | 20 Claims |
| 8. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first
semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the
layer of insulator, the method comprising the steps of:
forming a shallow trench isolation region extending through the second semiconductor layer to the layer of insulator;
forming a mask comprising polycrystalline silicon overlying the shallow trench isolation region, the mask comprising a first
opening and a second opening;
implanting first type conductivity determining ions into the first semiconductor layer through the first opening to form a
first impurity doped region and second type conductivity determining ions into the first semiconductor layer through the second
opening to form a second impurity doped region; and
forming a first electrical contact to the first impurity doped region and a second electrical contact to the second impurity
doped region.
|