| US 7,463,530 B2 | ||
| Operating method of non-volatile memory device | ||
| Hang-Ting Lue, Hsinchu (Taiwan); Erh-Kun Lai, Hsinchu (Taiwan); and Szu-Yu Wang, Hsinchu (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Oct. 30, 2006, as Appl. No. 11/554,455. | ||
| Claims priority of application No. 95122001 A (TW), filed on Jun. 20, 2006. | ||
| Prior Publication US 2007/0290273 A1, Dec. 20, 2007 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.24 [365/185.28] | 18 Claims |
| 1. An operating method of a memory cell, the operating method comprising:
providing a memory cell, the memory cell comprising:
a substrate, having two source/drain regions being separated by a channel region disposed under a surface of the substrate;
an insulating layer, disposed on the channel region;
a charge storage layer, disposed on the insulating layer;
a multi-layer tunneling dielectric structure, disposed on the charge storage layer; and
a gate, disposed on the multi-layer tunneling dielectric structure;
performing a first operation, supplying a negative bias to the gate and setting the source/drain regions to be floating, grounded,
or 0V, injecting electrons from the gate of the memory cell into the charge storage layer through the multi-layer tunneling
dielectric structure by −FN tunneling so as to increase the threshold voltage of the memory cell; and
performing a second operation, supplying a positive bias to the gate and setting the source/drain regions to be floating,
grounded, or 0V, injecting holes from the gate of the memory cell to the charge storage layer through the multi-layer tunneling
dielectric structure by +FN tunneling so as to decrease the threshold voltage of the memory cell.
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