| US 7,463,067 B2 | ||
| Switch block for FPGA architectures | ||
| Luca Ciccarelli, Rimini (Italy); Andrea Lodi, Castel S. Pietro (Italy); Roberto Giansante, Pescara (Italy); Luca Magagni, Bologna (Italy); Roberto Canegallo, Rimini (Italy); and Roberto Guerrieri, Bologna (Italy) | ||
| Assigned to STMicroelectronics S.r.l., Agrate Brianza (Italy) | ||
| Filed on Oct. 02, 2006, as Appl. No. 11/537,781. | ||
| Claims priority of provisional application 60/722672, filed on Sep. 30, 2005. | ||
| Prior Publication US 2007/0085563 A1, Apr. 19, 2007 | ||
| Int. Cl. H03K 19/094 (2006.01) | ||
| U.S. Cl. 326—113 [326/98] | 40 Claims |
| 1. A switch block connecting a first, second, third and fourth lines and comprising:
a first pass-transistor connected between the first line and a first internal node;
a second pass-transistor connected between the second line and the first internal node;
a third pass-transistor connected between the third line and the first internal node;
a fourth pass-transistor connected between the fourth line and a second internal node;
a first inverter and a second inverter, inserted between the first and the second internal node and interconnected at a third
internal node;
the first inverter comprising a PMOS transistor and an NMOS transistor connected in series to each other and between the first
voltage reference and a fourth internal node, the transistors of the first inverter having their gate terminals connected
to each other and to the first internal node and common drain terminals connected to the third internal node;
the second inverter comprising a PMOS transistor and an NMOS transistor connected in series to each other and between the
first voltage reference and the fourth internal node, the transistors of the second inverter having their gate terminals connected
to each other and to the third internal node and common drain terminals connected to the second internal node; and
wherein the fourth internal node is connected to a second voltage reference by means of a pull-down block.
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