| US 7,463,060 B1 | ||
| Programmable logic device and method of testing | ||
| Trent Whitten, Beaverton, Oreg. (US); and Kam Fai So, Beaverton, Oreg. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Jun. 13, 2006, as Appl. No. 11/452,714. | ||
| Int. Cl. H03K 19/173 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—40 [326/38; 326/46] | 16 Claims |
| 1. A programmable logic device, comprising:
a plurality of programmable resources;
non-volatile configuration to store configuration data for configuring the plurality of programmable resources; and
test-override circuitry operable to determine a test mode and selectively operable dependent upon the test mode determination
to override by bypassing the configuration data stored in the non-volatile configuration memory and configure at least one
of the plurality of programmable resources based on test data of a source different from the configuration data stored in
the non-volatile configuration memory.
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