| US 7,463,059 B2 | ||
| Alterable application specific integrated circuit (ASIC) | ||
| Raminda Udaya Madurawe, Sunnyvale, Calif. (US) | ||
| Assigned to Tier-Logic, Inc., Santa Clara, Calif. (US) | ||
| Filed on Mar. 10, 2008, as Appl. No. 12/45,635. | ||
| Application 12/045635 is a continuation of application No. 11/400122, filed on Apr. 10, 2006, granted, now 7,345,505. | ||
| Application 11/400122 is a continuation in part of application No. 10/267483, filed on Oct. 08, 2002. | ||
| Claims priority of provisional application 60/393763, filed on Jul. 08, 2002. | ||
| Claims priority of provisional application 60/397070, filed on Jul. 22, 2002. | ||
| Prior Publication US 2008/0150579 A1, Jun. 26, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/173 (2006.01) | ||
| U.S. Cl. 326—38 [326/41] | 20 Claims |
| 1. A semiconductor device, comprising:
a plurality of circuit blocks configurable to execute a plurality of applications; and
a configuration circuit coupled to the plurality of circuit blocks to program the circuit blocks, the configuration circuit
comprising a plurality of memory elements, the memory elements further comprising:
a first set of memory elements to store a first application instruction; and
a second set of memory elements to store a second application instruction; and
a global control signal to select the first or second application instruction in the configuration circuit to program the
circuit blocks to execute one of the stored applications.
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