| US 7,462,521 B2 | ||
| Dual-gate device and method | ||
| Andrew J. Walker, 1638 Cornell Dr., Mountain View, Calif. 94040 (US); and Maitreyee Mahajani, 20255 Knollwood Dr., Saratoga, Calif. 95070 (US) | ||
| Filed on Nov. 29, 2004, as Appl. No. 11/114. | ||
| Prior Publication US 2006/0115939 A1, Jun. 01, 2006 | ||
| Int. Cl. H01L 21/338 (2006.01) | ||
| U.S. Cl. 438—176 [438/238; 438/381; 438/257; 438/951; 257/E21.304; 257/E21.645; 257/E21.646; 257/E21.623; 257/E21.658] | 16 Claims |
| 1. A method for providing a dual-gate semiconductor device, comprising:
providing a first insulating layer over a semiconductor substrate;
forming a first gate electrode structure over the insulating layer;
forming a first dielectric layer over the first gate electrode structure;
forming a semiconductor layer over the first dielectric layer, such that the first gate electrode structure, the first dielectric
layer and a portion of a surface of the semiconductor layer form a first semiconductor device;
forming a second dielectric layer over the semiconductor layer; and
forming a second gate electrode structure over the second dielectric layer, such that the second gate electrode structure,
the second dielectric layer and a portion of a surface of the semiconductor layer form a second semiconductor device, and
such that the first and second semiconductor devices are sufficiently isolated from each other from electrostatically interacting.
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