CPC G06T 15/04 (2013.01) [G06F 9/3877 (2013.01); G06F 9/3885 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06T 17/10 (2013.01); G06T 17/20 (2013.01)] | 20 Claims |
1. A graphics processing unit comprising a computation unit implemented in hardware logic, the computation unit comprising:
a plurality of inputs arranged to receive one or more input values and a plurality of sum-of-products (SOP) coefficients, the plurality of SOP coefficients comprising coefficients relating to a plurality of different SOPs;
a datapath block comprising one or more computation pipelines; and
a control block comprising a plurality of sequencers;
wherein each sequencer comprises a plurality of hard-coded micro-programs and hardware logic arranged to select one of the micro-programs based on one or more control inputs, wherein each micro-program defines a sequence of operations to be performed by the pipelines in the datapath block as part of a SOP computation and different micro-programs implement different SOPs.
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