US 11,836,845 B2
Texture filtering with dynamic scheduling in computer graphics
Casper Van Benthem, Abbots Langley (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Nov. 30, 2021, as Appl. No. 17/538,933.
Application 17/538,933 is a continuation of application No. 16/800,242, filed on Feb. 25, 2020, granted, now 11,200,723, issued on Dec. 14, 2021.
Application 16/800,242 is a continuation of application No. 16/370,493, filed on Mar. 29, 2019, granted, now 10,614,610, issued on Apr. 7, 2020.
Claims priority of application No. 1805637 (GB), filed on Apr. 5, 2018.
Prior Publication US 2022/0084276 A1, Mar. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/04 (2011.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 17/10 (2006.01); G06T 17/20 (2006.01)
CPC G06T 15/04 (2013.01) [G06F 9/3877 (2013.01); G06F 9/3885 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06T 17/10 (2013.01); G06T 17/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processing unit comprising a computation unit implemented in hardware logic, the computation unit comprising:
a plurality of inputs arranged to receive one or more input values and a plurality of sum-of-products (SOP) coefficients, the plurality of SOP coefficients comprising coefficients relating to a plurality of different SOPs;
a datapath block comprising one or more computation pipelines; and
a control block comprising a plurality of sequencers;
wherein each sequencer comprises a plurality of hard-coded micro-programs and hardware logic arranged to select one of the micro-programs based on one or more control inputs, wherein each micro-program defines a sequence of operations to be performed by the pipelines in the datapath block as part of a SOP computation and different micro-programs implement different SOPs.