CPC G06F 7/5443 (2013.01) [G06F 7/483 (2013.01); G06F 7/533 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3016 (2013.01); G06F 9/30112 (2013.01); G06F 2207/3812 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01)] | 17 Claims |
1. A processor comprising:
a decoder to decode an instruction specifying an operation, the instruction comprising a first operand and a second operand;
control circuitry, responsive to a precision of the first and second operands being at or above a threshold, to cause a first multiplication circuitry to process a first value and a second value indicated by the first operand and the second operand, respectively, to generate a result, the processing of the first and second values to generate the result including multiplication, and responsive to the precision of the first and second operands being below the threshold, to cause a second multiplication circuitry to process the first and second values indicated by the first operand and the second operand, respectively, to generate the result; and
adder circuitry to add the result to an accumulated value to generate a new accumulated value.
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