US 11,836,464 B2
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
Aditya Varma, Uttar Pradesh (IN); and Michael Espig, Newberg, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Jun. 14, 2022, as Appl. No. 17/839,905.
Application 17/839,905 is a continuation of application No. 16/919,022, filed on Jul. 1, 2020, granted, now 11,366,636.
Application 16/919,022 is a continuation of application No. 16/160,853, filed on Oct. 15, 2018, granted, now 10,713,012, issued on Jul. 14, 2020.
Prior Publication US 2022/0342641 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/544 (2006.01); G06F 7/533 (2006.01); G06F 9/30 (2018.01); G06F 7/483 (2006.01); G06N 3/063 (2023.01); G06N 3/045 (2023.01)
CPC G06F 7/5443 (2013.01) [G06F 7/483 (2013.01); G06F 7/533 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3016 (2013.01); G06F 9/30112 (2013.01); G06F 2207/3812 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
a decoder to decode an instruction specifying an operation, the instruction comprising a first operand and a second operand;
control circuitry, responsive to a precision of the first and second operands being at or above a threshold, to cause a first multiplication circuitry to process a first value and a second value indicated by the first operand and the second operand, respectively, to generate a result, the processing of the first and second values to generate the result including multiplication, and responsive to the precision of the first and second operands being below the threshold, to cause a second multiplication circuitry to process the first and second values indicated by the first operand and the second operand, respectively, to generate the result; and
adder circuitry to add the result to an accumulated value to generate a new accumulated value.