| US 7,461,308 B2 | ||
| Method for testing semiconductor chips by means of bit masks | ||
| Jochen Kallscheuer, Munich (Germany); Udo Hartmann, Neuried (Germany); and Patric Stracke, Munich (Germany) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Nov. 28, 2005, as Appl. No. 11/287,605. | ||
| Claims priority of application No. 10 2004 057 483 (DE), filed on Nov. 29, 2004. | ||
| Prior Publication US 2006/0156107 A1, Jul. 13, 2006 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—726 [714/5; 714/25; 714/30; 714/42; 714/709; 714/715; 714/718; 714/719; 714/720; 714/722; 714/724; 714/727; 714/728; 714/729; 714/733; 714/734; 714/736; 714/738; 714/739; 714/742; 714/745; 365/201] | 22 Claims |
| 1. A method for testing semiconductor chips comprising:
providing a chip having at least one first register set having a plurality of registers and at least one second register set
having a plurality of registers, at least one register of the first register set and at least one register of the second register
set being 1:1 logically combined with one another;
storing a first serial bit string, the bit sequence of which can be assigned to at least one test mode, in the first register
set;
transmitting a bit sequence for application of the logical combination between the at least one register of the first register
set and the at least one register of the second register set to the first serial bit string stored in the first register set;
and
reading out test results or a status of the test modes by means of a second serial bit string.
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