| US 7,460,427 B2 | ||
| Semiconductor integrated circuit device | ||
| Koichi Kawakami, Yokohama (Japan); and Hiroshi Nakamura, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 24, 2005, as Appl. No. 11/209,730. | ||
| Claims priority of application No. 2004-252673 (JP), filed on Aug. 31, 2004. | ||
| Prior Publication US 2006/0044917 A1, Mar. 02, 2006 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—225 [365/189.09; 365/185.11] | 24 Claims |
| 1. A semiconductor integrated circuit device comprising:
an ID code memory circuit configured to store ID code data bits in a non-volatile manner;
an ID code generating circuit configured to generate an ID code based on the data bits stored in the ID code memory circuit
and output it to an external terminal;
a power supply voltage detecting circuit configured to detect a power supply voltage supplied from the external and supply
a select signal to at least one of the ID code memory circuit and ID code generating circuit for selectively generating one
of ID codes, data bits of which are different from each other at least in part in correspondence with power supply voltage
levels.
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