| US 7,460,421 B2 | ||
| Semiconductor integrated circuit device | ||
| Koji Kohara, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 16, 2007, as Appl. No. 11/623,602. | ||
| Claims priority of application No. 2006-010082 (JP), filed on Jan. 18, 2006. | ||
| Prior Publication US 2007/0165467 A1, Jul. 19, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—200 [365/230.06] | 20 Claims |
| 1. A semiconductor integrated circuit comprising:
a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and
transferred with data of a defect address of a semiconductor memory and store the data of the defect address;
a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy
data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy
data in a form of set; and
a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile
memory elements in accordance with the address data showing the memory macro as the transfer destination.
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