| US 7,460,402 B2 | ||
| Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages | ||
| Noboru Shibata, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 07, 2006, as Appl. No. 11/447,983. | ||
| Claims priority of application No. 2005-168290 (JP), filed on Jun. 08, 2005. | ||
| Prior Publication US 2006/0279993 A1, Dec. 14, 2006 | ||
| Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.03; 365/185.24] | 20 Claims |
| 1. A semiconductor memory device comprising:
a memory cell which stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number);
a storage section which stores a plurality of items of parameter data for generating the threshold levels;
an arithmetic circuit which calculates voltage data for generating voltages corresponding to the threshold levels by accumulating
the parameter data read from the storage section; and
a voltage generating circuit which generates a voltage on the basis of the voltage data calculated by the arithmetic circuit,
wherein the arithmetic circuit, when reading data from the memory cell at threshold level k (k<=n), generates the voltage
data by accumulating parameter data at the threshold levels i to k (i<=k).
|