| US 7,460,385 B2 | ||
| Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof | ||
| Wolfgang Gruber, Neu-Esting (Germany); Ronald Kakoschke, München (Germany); Thomas Schweizer, Ebersberg (Germany); and Dominik Wegertseder, Haar (Germany) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Oct. 14, 2005, as Appl. No. 11/251,355. | ||
| Application 11/251355 is a continuation of application No. PCT/EP2004/050322, filed on Mar. 17, 2004. | ||
| Claims priority of application No. 103 19 271 (DE), filed on Apr. 29, 2003. | ||
| Prior Publication US 2006/0077723 A1, Apr. 13, 2006 | ||
| Int. Cl. G11C 5/02 (2006.01); G11C 5/06 (2006.01) | ||
| U.S. Cl. 365—51 [365/63] | 16 Claims |
| 1. A memory circuit arrangement comprising:
a cell array substrate, which has an integrated memory cell array contained in a memory circuit, the integrated memory cell
array including memory cells;
a logic circuit substrate, which has an integrated logic circuit that controls access to the memory cells, the logic circuit
substrate being a different substrate than the cell array substrate;
the logic circuit substrate has a circuit arrangement of a processor which is suitable for processing program instructions,
and the cell array substrate has an analog circuit;
wherein the logic circuit substrate has a sense amplifier, with the aid of which a memory state of a memory cell of the memory
cell array can be determined;
wherein the logic circuit includes at least one of:
a control circuit contained in the memory circuit, the control circuit controlling sequences when at least one of reading
or writing content of a memory cell of the memory cell array, or
a decoding circuit contained in the memory circuit, the decoding circuit selects, in a manner dependent on an address datum,
a word line or a bit line connected to a plurality of memory cells of the memory cell array.
|