| US 7,460,100 B2 | ||
| Liquid crystal display apparatus having level conversion circuit | ||
| Hideo Sato, Hitachi (Japan); Yoshiro Mikami, Hitachi (Japan); Hiroshi Kageyama, Hitachi (Japan); and Tatsuya Ohkubo, Chigasaki (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Jun. 09, 2005, as Appl. No. 11/148,260. | ||
| Application 11/148260 is a continuation of application No. 10/797013, filed on Mar. 11, 2004, granted, now 6,919,873. | ||
| Application 10/797013 is a continuation of application No. 10/150952, filed on May 21, 2002, granted, now 6,714,184. | ||
| Application 10/150952 is a continuation of application No. 09/337260, filed on Jun. 22, 1999, granted, now 6,392,625. | ||
| Claims priority of application No. 10-192389 (JP), filed on Jun. 23, 1998. | ||
| Prior Publication US 2006/0007216 A1, Jan. 12, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G09G 3/36 (2006.01) | ||
| U.S. Cl. 345—98 [345/94; 345/95; 345/100; 345/211] | 18 Claims |
| 1. A display apparatus comprising:
a display unit comprised of pixel elements arranged in a matrix;
a signal circuit and a scanning circuit for driving the pixel elements;
a first type level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform
level conversion of data signals and transmit to the signal circuit and the scanning circuit to drive the pixel elements;
and
a second level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform level
conversion of differential clock signals to control the transmission of data signals to the signal circuit to drive the pixel
elements,
wherein a differential input type level conversion circuit includes a level conversion unit comprising:
a first transistor and a second transistor connected in parallel, having respective gate electrodes coupled to receive a bias
voltage; and
a first resistance element and a second resistance element connected in parallel, and disposed between respective drain electrodes
of the first transistor and the second transistor and a power supply terminal;
wherein respective source electrodes of the first transistor and the second transistor are coupled to receive clock signals
having a mutually different polarity and a low voltage amplitude, and the respective drain electrodes of the first transistor
and the second transistor are coupled to output clock signals having a mutually different polarity and a high voltage amplitude.
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