| US 7,460,099 B2 | ||
| Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power | ||
| Yasushi Kubota, Sakurai (Japan); Hajime Washio, Tenri (Japan); Ichiro Shiraki, Tenri (Japan); Kazuhiro Maeda, Tenri (Japan); and Yasuyoshi Kaise, Tenri (Japan) | ||
| Assigned to Sharp Kabushiki Kaisha, Osaka (Japan) | ||
| Filed on Sep. 23, 2004, as Appl. No. 10/949,990. | ||
| Application 10/949990 is a division of application No. 09/506033, filed on Feb. 16, 2000, granted, now 7,196,699. | ||
| Application 09/506033 is a continuation in part of application No. 09/300178, filed on Apr. 27, 1999, granted, now 6,580,411. | ||
| Claims priority of application No. 10-117955 (JP), filed on Apr. 28, 1998; application No. 10-364774 (JP), filed on Dec. 22, 1998; application No. 11-36778 (JP), filed on Feb. 16, 1999; application No. 11-105236 (JP), filed on Apr. 13, 1999; and application No. 11-129533 (JP), filed on May 11, 1999. | ||
| Prior Publication US 2005/0057556 A1, Mar. 17, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G09G 3/36 (2006.01); G09G 5/00 (2006.01) | ||
| U.S. Cl. 345—98 [345/99; 345/100; 345/211] | 16 Claims |
| 1. A CMOS logical circuit for use in a liquid crystal display device, the CMOS logical circuit synchronizing a pulse signal
for latching image data with a clock signal, the CMOS logical circuit comprising:
a first input terminal into which the pulse signal is inputted, the pulse signal being inputted from the first input terminal
to a gate electrode of a first transistor;
a second input terminal into which the clock signal is inputted, the clock signal being inputted from the second input terminal
to a gate electrode of a second transistor; and
an output terminal from which a synchronized pulse signal is outputted, wherein the clock signal has an amplitude smaller
than an amplitude of the synchronized pulse signal of the CMOS logical circuit to reduce power consumption.
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