| US 7,460,042 B2 | ||
| Encoding circuit, decoding circuit, encoder circuit, decoder circuit, and CABAC processing method | ||
| Makoto Oshikiri, Ome (Japan); and Ryuji Sakai, Hanno (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 27, 2007, as Appl. No. 11/819,391. | ||
| Claims priority of application No. 2006-179905 (JP), filed on Jun. 29, 2006. | ||
| Prior Publication US 2008/0001796 A1, Jan. 03, 2008 | ||
| Int. Cl. H03M 7/00 (2006.01) | ||
| U.S. Cl. 341—107 [341/50] | 17 Claims |
| 1. An encoding circuit comprising:
a taking-over unit which takes over probability tables of divided regions of a previous frame image of a frame image having
N divided regions continuously given at predetermined intervals to divided regions of a present frame image, respectively;
an acquiring unit which acquires a parameter of an adjacent macro block of the previous frame image in calculation of a parameter
of a macro block serving as a processing unit in the divided region when the macro block is located on a boundary between
the divided regions;
a selecting unit which calculates the acquired parameter of the adjacent macro block to select one of probability models in
the probability table; and
an encoding unit which arithmetically encodes a residual signal in the frame image on the basis of the selected probability
model to generate an encoded bit string.
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