a voltage control delay line for receiving a reference clock signal and for delaying said reference clock signal to provide a feedback clock signal;

a phase detector for receiving said reference clock signal, an additional reference signal, and said feedback clock signal, said phase detector generating a charge down control signal having a first duration of time in response to a first edge of said reference clock signal, a charge up control signal having a second duration of time in response to an edge of the feedback clock signal occurring within less than 180 degrees from said first edge, the first duration of time being substantially similar to a first time between the first edge of the reference clock signal and the edge of the feedback clock signal, the second duration of time being substantially similar to a second time between the edge of the feedback clock signal and a midway signal edge occurring between the first edge and a subsequent edge of the reference clock signal;

a loop filter including a capacitor, for providing a variable bias voltage for selecting a delay to be added to said reference clock signal by said voltage control delay line; and

a charge pump including at least two switching transistors, one of the switching transistors permitting current to be added into said capacitor when switched on in response to said charge up signal, another of said switching transistors permitting current to be removed from said capacitor when switched on in response to said charge down signal.