US 7,459,945 B2
Gate driving circuit and gate driving method of power MOSFET
Ichiro Omura, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jul. 27, 2005, as Appl. No. 11/189,704.
Claims priority of application No. 2004-234085 (JP), filed on Aug. 11, 2004.
Prior Publication US 2006/0034114 A1, Feb. 16, 2006
Int. Cl. H03K 3/00 (2006.01)
U.S. Cl. 327—108  [327/109; 327/110] 26 Claims
OG exemplary drawing
 
1. A gate driving circuit of a power MOSFET, comprising:
a first capacitance element connected in series between a first higher voltage terminal and a first lower voltage terminal;
a first switch connected in series between said first higher voltage terminal and a first node;
a second switch connected in series between said first node and first lower voltage terminal;
a first diode connected in parallel with said first switch, and having a cathode connected to said first higher voltage terminal and an anode connected to said first node;
a second diode connected in parallel with said second switch, and having a cathode connected to said first node and an anode connected to said first lower voltage terminal;
an inductance element connected in series between said first node and a second node;
a third switch connected in series between said first higher voltage terminal and second node;
a fourth switch connected in series between said second node and first lower voltage terminal;
a third diode connected in parallel with said third switch, and having a cathode connected to said first higher voltage terminal and an anode connected to said second node;
a fourth diode connected in parallel with said fourth switch, and having a cathode connected to said second node and an anode connected to said first lower voltage terminal; and
a switching control circuit which controls ON/OFF operations of each of said first, second, third, and fourth switches,
wherein in order to drive a power MOSFET having a drain and source connected between a second higher voltage terminal and a second lower voltage terminal, and a gate connected to said second node,
said switching control circuit performs switching control such that a period during which said first and fourth switches are simultaneously ON and said fourth switch is turned OFF while said first switch remains ON exists prior to turning on said power MOSFET, and
performs switching control such that another period during which said second and third switches are simultaneously ON exists prior to turning OFF said power MOSFET.