| US 7,459,771 B2 | ||
| Assembly structure for electronic power integrated circuit formed on a semiconductor die and corresponding manufacturing process | ||
| Paolo Casati, Sesto S. Giovanni (Italy); Amedeo Maierna, Albuzzano (Italy); and Bruno Murari, Monza (Italy) | ||
| Assigned to STMicroelectronics, S.R.L., Agrate Brianza (Italy) | ||
| Filed on Feb. 18, 2003, as Appl. No. 10/369,114. | ||
| Claims priority of application No. 02425079 (EP), filed on Feb. 18, 2002. | ||
| Prior Publication US 2003/0209783 A1, Nov. 13, 2003 | ||
| Int. Cl. H01L 23/495 (2006.01) | ||
| U.S. Cl. 257—676 [257/675; 257/672] | 4 Claims |
| 1. An integrated circuit, comprising:
a semiconductor die having a first side and a contact pad disposed on the first side;
a lead welded to and in electrical connection with the contact pad and having a welded portion spaced a first distance from
the first side of the die, wherein the welded portion of the lead is unencapsulated; and
an electromagnetic shield not overlapping the contact pad and thermally coupled to the first side of the semiconductor die
by an adhesive layer with no electrical interconnects to the shield and the die through the adhesive layer and spaced a second
distance from the first side of the die, the second distance greater than or equal to the first distance.
|