| US 7,459,751 B2 | ||
| Insulated gate semiconductor device with small feedback capacitance and manufacturing method thereof | ||
| Koichi Sugiyama, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 01, 2005, as Appl. No. 11/216,014. | ||
| Claims priority of application No. 2004-259206 (JP), filed on Sep. 07, 2004. | ||
| Prior Publication US 2006/0049456 A1, Mar. 09, 2006 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—340 [257/E29.006] | 14 Claims |
| 1. An insulated gate semiconductor device, comprising:
a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;
a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first
insulating film region between the semiconductor region and the gate electrode region; and
a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being
adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film
region to separate the conductor region from the semiconductor region,
wherein the first region is buried in first groove-like removed portions of the semiconductor region; and
wherein the second region is buried in second groove-like removed portions of the semiconductor region, and provided to oppose
at least the channel forming region of the semiconductor region through the first region.
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