| US 7,459,748 B2 | ||
| Semiconductor memory device | ||
| Riichiro Shirota, Fujisawa (Japan); Fumitaka Arai, Yokohama (Japan); Toshiyuki Enda, Zushi (Japan); Hiroyoshi Tanimoto, Yokohama (Japan); Naoki Kusunoki, Fuchu (Japan); Nobutoshi Aoki, Yokohama (Japan); Makoto Mizukami, Kawasaki (Japan); Kiyotaka Miyano, Shinagawa-ku (Japan); and Ichiro Mizushima, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 16, 2006, as Appl. No. 11/549,770. | ||
| Claims priority of application No. 2005-301906 (JP), filed on Oct. 17, 2005; and application No. 2006-160500 (JP), filed on Jun. 09, 2006. | ||
| Prior Publication US 2007/0102749 A1, May 10, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—314 [257/E21.209] | 13 Claims |
| 1. A semiconductor memory device comprising:
a semiconductor substrate;
a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor
layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and
a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells
connected in series and first and second select gate transistors disposed at both ends thereof,
wherein the semiconductor layer is a crystalline layer epitaxially grown from a seed crystal area in the semiconductor substrate,
which is in contact with the semiconductor layer via the opening.
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