| US 7,459,743 B2 | ||
| Dual port gain cell with side and top gated read transistor | ||
| Jack A. Mandelman, Flat Rock, N.C. (US); Kangguo Cheng, Beacon, N.Y. (US); Ramachandra Divakaruni, Ossining, N.Y. (US); Carl J. Radens, LaGrangeville, N.Y. (US); and Geng Wang, Stormville, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Aug. 24, 2005, as Appl. No. 11/161,962. | ||
| Prior Publication US 2007/0047293 A1, Mar. 01, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01) | ||
| U.S. Cl. 257—300 [257/301; 257/304; 257/E27.092] | 20 Claims |
| 1. A memory cell comprising:
a first transistor having a gate, a first source, and a first drain;
a second transistor having a first gate, a second gate, a second source, and a second drain;
a trench located in a semiconductor-on-insulator (SOI) substrate including a stack of, from top to bottom, a semiconductor-on-insulator
(SOI) layer, a buried insulator layer, and a bottom substrate layer; and
a capacitor having a first terminal and a storage node dielectric, wherein said first terminal of said capacitor and said
second gate of said second transistor comprise a single entity and located in said trench, and wherein said storage node dielectric
laterally abuts said SOI layer, said buried insulator layer, and said bottom substrate layer at sidewalls of said trench.
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