| US 7,459,741 B2 | ||
| Semiconductor memory device | ||
| Masaru Kidoh, Kawasaki (Japan); Hideaki Aochi, Kawasaki (Japan); Ryota Katsumata, Yokohama (Japan); and Masaru Kito, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 28, 2006, as Appl. No. 11/390,255. | ||
| Claims priority of application No. 2006-008830 (JP), filed on Jan. 17, 2006. | ||
| Prior Publication US 2007/0164340 A1, Jul. 19, 2007 | ||
| Int. Cl. H01L 29/34 (2006.01) | ||
| U.S. Cl. 257—296 [257/297; 257/298; 257/299; 257/310; 257/311; 257/312; 257/313; 257/314; 257/315; 257/316] | 20 Claims |
| 10. A semiconductor memory device comprising:
a plurality of trenches disposed in a semiconductor substrate;
a transistor including a drain, a channel region, and a source disposed in a columnar semiconductor substrate area held between
the trenches, and a gate electrode disposed through a gate insulator on one side face of the channel region and disposed in
a trench;
a capacitor directly connected to the other side face of the channel region and disposed in another trench;
a first wiring line electrically connected to the gate electrode; and
a second wiring line electrically connected to the drain.
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