a semiconductor substrate;

a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner, bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of the matrix;

a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays;

first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and

third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit, wherein

the memory cell comprises a variable resistance element for storing as information a resistance value, and wherein the variable resistance element includes:

a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and

electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.