| US 7,459,384 B2 | ||
| Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | ||
| Paul D. Agnello, Wappingers Falls, N.Y. (US); Rajeev Malik, Pleasantville, N.Y. (US); and K. Paul Muller, Wappingers Falls, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 28, 2004, as Appl. No. 10/710,227. | ||
| Prior Publication US 2005/0287798 A1, Dec. 29, 2005 | ||
| Int. Cl. H01L 21/4763 (2006.01); H01L 21/3205 (2006.01) | ||
| U.S. Cl. 438—595 [438/639; 438/640; 438/643] | 15 Claims |
| 1. A method of preventing interlayer dielectric cavitation between a pair of structures having a high aspect ratio region
therebetween in a semiconductor device, the method comprising:
depositing a first dielectric in the high aspect ratio region;
removing the first dielectric to form a bearing surface adjacent each structure, wherein the bearing surface is inclined to
a spacer of each structure and extends continuously upwards from a surface coplanar with the base of each structure terminating
at a first portion along the height of the spacer of each structure and wherein the remaining first dielectric of the bearing
surface partially fills an undercut of each structure;
depositing a barrier layer over each structure including respective bearing surfaces, a second portion along the height of
the spacer of each structure, and the high aspect ratio region between the structures; and
filling the high aspect ratio region with an interlayer dielectric after the depositing of the barrier layer.
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