| US 7,458,057 B2 | ||
| Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern | ||
| Toshiya Kotani, Machida (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 02, 2004, as Appl. No. 10/882,217. | ||
| Claims priority of application No. 2003-190341 (JP), filed on Jul. 02, 2003. | ||
| Prior Publication US 2005/0031976 A1, Feb. 10, 2005 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—21 [716/19] | 12 Claims |
| 1. A pattern correction method in which a shape of a target pattern is corrected in accordance with an arrangement state between
the target pattern configuring a designed pattern and a vicinity pattern disposed in the vicinity of the target pattern, the
pattern correction method comprising:
detecting a first arrangement state between a first predetermined portion of an edge of the target pattern and the vicinity
pattern;
detecting a second arrangement state between a second predetermined portion of the edge of the target pattern and the vicinity
pattern;
determining a correction value of the edge of the target pattern based on a rule in accordance with the first and second arrangement
states; and
adding the correction value to the edge of the target pattern, wherein:
the first and second arrangement states are indicated by a distance between the edge of the target pattern and the edge of
the vicinity pattern existing in a direction crossing the edge of the target pattern at right angles; and
determining the correction value is performed by determining a first correction value in a case where the first arrangement
state is equal to the second arrangement state, and determining a second correction value in a case where the second arrangement
state is larger than the first arrangement state, and the second correction value is smaller than the first correction value.
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