US 7,458,022 B2
Hardware/software partition for high performance structured data transformation
Karempudi V. Ramarao, Austin, Tex. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Jul. 12, 2004, as Appl. No. 10/889,614.
Claims priority of provisional application 60/513306, filed on Oct. 22, 2003.
Prior Publication US 2005/0091589 A1, Apr. 28, 2005
Int. Cl. G06F 17/00 (2006.01)
U.S. Cl. 715—236  [707/6] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a computer accessible medium encoded with a plurality of instructions which, when executed, compile a stylesheet into one or more data structures, wherein the data structures include one or more expression trees representing expressions in the stylesheet, wherein the expressions select nodes in a corresponding source document tree structure and further wherein each expression has a corresponding body that specifies a portion of an output document structure to be instantiated for each matching node; and
a hardware circuit coupled to receive the data structures and a document, wherein the hardware circuit is configured to perform at least a portion of transforming the document as specified in the stylesheet using the data structures and wherein the hardware circuit is configured to apply the expressions represented in the expression trees to the document to identify nodes in the document that satisfy the expressions, and further wherein the hardware circuit is configured to cause the transformed document to be stored in a memory device, wherein the plurality of instructions, when executed, assign serial numbers to each node identifier in the stylesheet, and wherein the data structures include one or more symbol tables stored in memory coupled with the hardware circuit that map the node identifiers to the serial numbers.