| US 7,458,008 B2 | ||
| Decision voting in a parallel decoder | ||
| Bo Wang, North Potomac, Md. (US); and Adrian R. Macias, Oceanside, Calif. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Dec. 30, 2004, as Appl. No. 11/24,803. | ||
| Prior Publication US 2006/0150056 A1, Jul. 06, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03M 13/00 (2006.01) | ||
| U.S. Cl. 714—796 [714/795] | 14 Claims |
| 1. An integrated circuit capable of conducting a decoding operation on a received sequence of n symbols associated with an
Ultra Wide Band (UWB) transmission, the received sequence presumed to include an encoded representation of a message sequence
of k symbols encoded according to a convolutional code of rate k/n having a constraint K and having 2M code states, where M is equal to K−1, the received sequence received according to a symbol rate associated with the message
sequence, the integrated circuit comprising:
a track buffer including 2M path registers configured to be capable of storing 2M path metrics associated with the output of 2M−1 parallel Add Compare Select (ACS) elements; and
a voting unit configured to be capable of generating a decision bit based on the contents of the 2M path registers by voting for the decision bit according to a voting protocol,
wherein each of the 2M path registers has a depth of around 100 to around 150 spin cycles.
|