| US 7,457,994 B2 | ||
| Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code | ||
| Yoshihiro Kikuchi, Yokohama (Japan); Toshiaki Watanabe, Yokohama (Japan); Kenshi Dachiku, Kawasaki (Japan); Takeshi Chujoh, Shibuya-Ku (Japan); and Takeshi Nagai, Higashi-Murayama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Kawasaki-shi (Japan) | ||
| Filed on May 05, 2006, as Appl. No. 11/418,105. | ||
| Application 10/279109 is a division of application No. 09/580430, filed on May 30, 2000, granted, now 6,493,838, filed on Dec. 10, 2002. | ||
| Application 09/580430 is a division of application No. 09/148164, filed on Sep. 04, 1998, granted, now 6,249,895, filed on Jun. 19, 2001. | ||
| Application 09/148164 is a division of application No. 08/720067, filed on Sep. 27, 1996, granted, now 5,862,153, filed on Jan. 19, 1999. | ||
| Application 11/418105 is a continuation of application No. 10/279109, filed on Oct. 24, 2002, granted, now 7,093,170. | ||
| Claims priority of application No. 1995-276993 (JP), filed on Sep. 29, 1995. | ||
| Prior Publication US 2006/0206787 A1, Sep. 14, 2006 | ||
| Int. Cl. H03M 13/05 (2006.01) | ||
| U.S. Cl. 714—701 | 3 Claims |
| 1. A coding apparatus, comprising:
coding means for coding an inputted bitstream by an error correction and/or detection code composed of information bits, check
bits and a stuffing code; and
bitstream assembling means for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality
of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits
at desired positions of the bitstream and arranging the check bits at positions other than the synchronization code insertion
positions in the bitstream, the stuffing code having the number of bits necessary to shift the position of the check bits,
and an interval of the synchronization code insertion positions being longer than a length of the synchronization code.
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