| US 7,457,941 B2 | ||
| Vector processing system | ||
| Stephen Barlow, Cambridge (United Kingdom); Neil Bailey, Cambridge (United Kingdom); Timothy Ramsdale, Cambridge (United Kingdom); David Plowman, Saffron Walder (United Kingdom); and Robert Swann, Cambridge (United Kingdom) | ||
| Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
| Filed on Jan. 03, 2006, as Appl. No. 11/324,494. | ||
| Application 11/324494 is a continuation of application No. 10/284194, filed on Oct. 31, 2002, granted, now 7,036,001. | ||
| Claims priority of application No. 0126133.8 (GB), filed on Oct. 31, 2002. | ||
| Prior Publication US 2006/0136700 A1, Jun. 22, 2006 | ||
| Int. Cl. G06F 15/80 (2006.01) | ||
| U.S. Cl. 712—222 [712/22] | 16 Claims |
| 1. An integrated circuit comprising:
a decode circuit for receiving a plurality of instructions wherein a first instruction comprises a first operation and a second
instruction comprising a second operation;
a processing unit for executing the first operation on a pair of input values and generating an output result, wherein the
output result is stored in a register file;
a plurality of pixel processors, wherein each pixel processor is arranged to receive one or more values from the register
file and implement the second operation on said one or more values to generate a respective result, and wherein each of the
plurality of pixel processors is identified by an index; and
a post-processor for receiving the results of the plurality of pixel processors and for using said results in a manner defined
by a modifier to return the index of one of the pixel processors.
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