US 7,457,921 B2
Write barrier for data storage integrity
Henry P Gabryjelski, Seattle, Wash. (US); Krishnan Varadarajan, Redmond, Wash. (US); Peter W Wieland, Seattle, Wash. (US); and Raju Ramanathan, Redmond, Wash. (US)
Assigned to Microsoft Corporation, Redmond, Wash. (US)
Filed on Feb. 23, 2005, as Appl. No. 11/64,491.
Prior Publication US 2006/0190510 A1, Aug. 24, 2006
Int. Cl. G06F 12/12 (2006.01)
U.S. Cl. 711—135  [711/134] 19 Claims
OG exemplary drawing
 
1. A system that facilitates storage of data, comprising:
a hardware component that stores the data that is input asynchronously; and
a write baiter component that receives multiple synchronize cache commands and combines them into a single set for processing against the hardware component to flush the cache only once, interrogates the hardware component for its device capabilities, dynamically selects instructions suitable for interfacing to the hardware component and employs the selected instructions to ensure data integrity during storage of the data, wherein the device capabilities include at least one of device type, command structure or interface communications.