| US 7,457,917 B2 | ||
| Reducing power consumption in a sequential cache | ||
| Satish Damaraju, El Dorado Hills, Calif. (US); Subramaniam Maiyuran, Gold River, Calif. (US); Peter Smith, Folsom, Calif. (US); and Navin Monteiro, Folsom, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 29, 2004, as Appl. No. 11/27,413. | ||
| Prior Publication US 2006/0143382 A1, Jun. 29, 2006 | ||
| Int. Cl. G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 1/00 (2006.01) | ||
| U.S. Cl. 711—118 [711/128; 713/300; 713/324] | 14 Claims |
| 8. A system comprising:
a dynamic random access memory to store information; and
a cache memory coupled to the dynamic random access memory comprising:
a plurality of banks, each bank having:
a data array;
a decoder coupled to the data array to select a set of the data array, the decoder to be enabled only if the data array is
selected for access, the decoder comprising a wordline decoder having a first set of logic gates to receive a most significant
portion of a set address, a second set of logic gates coupled to an output of the first set of logic gates, and a third set
of logic gates coupled to an output of the second set of logic gates and an output of gating logic, and a column decoder to
receive a least significant portion of the set address and the output of the gating logic;
a sense amplifier coupled to the data array to read data output from the data array;
a status array associated with the plurality of banks, the status array to store early way information, wherein the early
way information corresponds to a way of a next set to be accessed and the early way information is to be used to gate the
decoder if the data array is not selected for access; and
a tag array associated wit the plurality of banks and separate from the status array and the data array, each entry of the
tag array to store a tag field, wherein the tag array is to be powered down during read access to a trace body.
|