| US 7,457,383 B2 | ||
| Receiving LSI device and receiver using the same | ||
| Shinichi Hasebe, Saitama-ken (Japan); and Masahiro Abe, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaish Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 23, 2005, as Appl. No. 11/159,338. | ||
| Claims priority of application No. 2004-185934 (JP), filed on Jun. 24, 2004. | ||
| Prior Publication US 2005/0286658 A1, Dec. 29, 2005 | ||
| Int. Cl. H04B 7/10 (2006.01); H04L 1/02 (2006.01) | ||
| U.S. Cl. 375—347 [375/267; 375/224] | 20 Claims |
| 1. A receiving large scale integrated circuit (LSI) device, comprising:
a demodulator which includes two signal processing circuits to demodulate two diversity signals to form a demodulated signal;
a decoder which decodes the demodulated signal in accordance with an error correcting code to form a decoded signal;
a receiving quality judgment circuit which codes the decoded signal to form a re-coded signal as a reference signal, compares
the demodulated signal with the reference signal to obtain an error rate of the two diversity signals and supplies a judgment
signal depending on the error rate; and
a control circuit which selects one of the two signal processing circuits or both two signal processing circuits in response
to the judgment signal of the receiving quality judgment circuit and stops supplying electric power or a clock signal to the
one of the two processing circuits not selected by the control circuit.
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