a clocked circuit having a clock input, an input, an output, a power supply connection, and a power return connection, wherein the clock input is operably coupled to receive a clock signal, wherein the clocked circuit provides an output signal at the output based on an input signal at the input and a transition of the clock signal, and wherein the power supply connection is operably coupled to a power supply and the power return is operably coupled to a circuit ground; and

an impedance trap circuit operably coupled to the power supply connection and the power return connection, wherein the impedance trap circuit attenuates a harmonic signal component of at least one of the input signal, the clock signal, and the output signal.