| US 7,457,357 B2 | ||
| Decision feedback equalizer design with interference removal and reduced error propagation | ||
| Rahul Garg, Haryana (India); Shobha Ramaswamy, Karnataka (India); and Aparna Chahrakodi Krishnashastry, Karnataka (India) | ||
| Assigned to Ittiam Systems (P) Ltd., Bangalore, Karnataka (India) | ||
| Filed on May 04, 2005, as Appl. No. 11/121,455. | ||
| Claims priority of provisional application 60/570707, filed on May 13, 2004. | ||
| Prior Publication US 2005/0254571 A1, Nov. 17, 2005 | ||
| Int. Cl. H03H 7/30 (2006.01); H03H 7/40 (2006.01) | ||
| U.S. Cl. 375—233 [375/229; 375/230; 375/231; 375/232] | 24 Claims |
| 1. A method of designing a decision feedback equalizer (DFE) for handling packet based complementary code keyed (CCK) symbols
comprising chips, the method comprising the steps:
providing an inter symbol interference (ISI) loop for addressing removal of ISI caused between said CCK symbols, using symbol
decisions;
providing an inter chip interference (ICI) loop for addressing removal of ICI caused between said chips of said CCK symbols
in said ICI loop, using chip decisions; and,
placing said ICI loop to be nested within said ISI loop such that said packet based CCK symbols first enter the ISI loop.
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