| US 7,457,150 B2 | ||
| Semiconductor memory | ||
| Kenji Tsuchida, Kawasaki (Japan); and Yoshihiro Ueda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 09, 2007, as Appl. No. 11/673,206. | ||
| Claims priority of application No. 2006-144484 (JP), filed on May 24, 2006. | ||
| Prior Publication US 2007/0279963 A1, Dec. 06, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—158 [365/63; 365/148] | 18 Claims |
| 1. A semiconductor memory comprising:
a first memory cell including a first resistance change element having a first end and a second end, a first FET and a second
FET, which is arranged in an even column;
a second memory cell including a second resistance change element having a first end and a second end, a third FET and a fourth
FET, which is arranged in an odd column;
a first bit line extending a column direction, which is connected to the first end of the first resistance change element;
a second bit line extending the column direction, wherein the first and second FETs connected in parallel between the second
end of the first resistance change element and the second bit line;
a third bit line extending the colunm direction, which is connected to the first end of the second resistance change element;
a fourth bit line extending the column direction, wherein the third and fourth FETs connected in parallel between the second
end of the second resistance change element and the fourth bit line;
a first word line extending a row direction, which is connected to a gate of the first FET;
a second word line extending the row direction, which is connected to gates of the second and third FETs; and
a third word line extending the row direction, which is connected to a gate of the fourth FET,
wherein an address mapping to the first to third word lines is based on one of a binary code or a gray code.
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