an internal circuit to be protected from an ESD voltage connected between a first power source terminal to which a predetermined voltage is applied and a second power source terminal to be energized;

a first MOS device which is logically controlled by the internal circuit and which configures a buffer circuit in which one of a drain and a source of the first MOS device is connected to an output terminal;

an ESD protective circuit having a discharge path connected between the output terminal and the second power source terminal and having a trigger terminal; and

a trigger circuit connected between the other of the drain and the source of the first MOS device and the trigger terminal of the ESD protective circuit;

wherein the first MOS device functions as the buffer circuit at a time of normal operation state when an ESD voltage is not applied, and when the ESD voltage is applied, the first MOS device makes a trigger current flow from the first MOS device to the ESD protective circuit via the trigger circuit; and

wherein a positive power source voltage is applied to the first power source terminal, the first MOS device is a first NMOS device, the buffer circuit includes a first PMOS device connected between the first power source terminal and the output terminal, and a second NMOS device which is connected between the output terminal and the second power source terminal, the trigger circuit includes a second PMOS device in which a source and a drain are connected between the source of the first NMOS device and the trigger terminal, and a gate connected to the first power source terminal, and the first NMOS device functions as a part of the buffer circuit at the time of normal operation state when an ESD voltage is not applied, and when the ESD voltage is applied, functions to generate a trigger current which flows from the first NMOS device to the ESD protective circuit via the second PMOS device.