a switching clock signal generating circuit configured to generate a switching clock signal based on an output clock signal;

a selection circuit that is supplied with a first clock signal and a second clock signal having different phases, a selection signal, and a switching signal to be changed based on the switching clock signal, and is configured to select one of the first clock signal and the second clock signal as an output signal according to the selection signal and to change output signal to the other one of the first clock signal and the second clock signal according to the switching signal; and

an output fixing circuit configured to receive the switching clock signal from the switching clock signal generating circuit, to change the switching signal based on the switching clock signal, and to supply the changed switching signal to the selection circuit, and configured to generate a pulse based on the switching signal and an output signal from the selection circuit which pulse is maintained at a high level or a low level during a period between a time when the output signal from the selection circuit falls or rises after the switching signal is changed and a time when the fallen or risen output signal from the selection circuit successively rises or falls, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.