| US 7,456,669 B2 | ||
| Semiconductor integrated circuit device | ||
| Chen Kong Teh, Tokyo (Japan); and Mototsugu Hamada, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 24, 2006, as Appl. No. 11/439,271. | ||
| Claims priority of application No. 2005-152901 (JP), filed on May 25, 2005; and application No. 2006-142134 (JP), filed on May 22, 2006. | ||
| Prior Publication US 2006/0267627 A1, Nov. 30, 2006 | ||
| Int. Cl. H03K 3/00 (2006.01) | ||
| U.S. Cl. 327—218 [327/199] | 20 Claims |
| 1. A semiconductor integrated circuit device, comprising:
a logic holding circuit having
an input terminal portion including two input terminals configured to receive a differential input signal, and
an output terminal portion including a terminal configured to output an output signal based on signals received by the two
input terminals, to output signals received by the two input terminals by a trigger signal to the output terminal portion
as the output signal, and to maintain a logic of the output signal;
a comparator configured to make a comparison between a logical value of the differential input signal and a logical value
of the output signal and to output two signals having logical values based on the comparison, each of the two signals outputted
as a voltage signal of low level or high level, wherein
the comparator is configured to output the voltage signals instead of the differential input signal to the input terminal
portion when the differential input signal does not vary a state of the output signal.
|