| US 7,456,615 B2 | ||
| Charging arrangement for capacitor means | ||
| Erkki Miettinen, Helsinki (Finland) | ||
| Assigned to ABB Oy, Helsinki (Finland) | ||
| Filed on Feb. 03, 2006, as Appl. No. 11/346,730. | ||
| Claims priority of application No. 20055052 (FI), filed on Feb. 04, 2005. | ||
| Prior Publication US 2006/0176027 A1, Aug. 10, 2006 | ||
| Int. Cl. H01M 10/46 (2006.01) | ||
| U.S. Cl. 320—166 | 14 Claims |
| 1. A charging arrangement for capacitor means, the arrangement being arranged to be supplied by a voltage containing network
cycles, and comprising a gate-controlled semiconductor switch (Tch) arranged for charging the capacitor means (Caux), and means for generating a control signal of the gate-controlled semiconductor switch, wherein the means for generating
the control signal include a clipper, a first integrator, a second integrator, a cycle indicator, a reset device, an adder,
a restricting circuit, a trigger circuit, and an isolation transformer, wherein
the clipper is arranged to restrict the supplying voltage containing network cycles to be substantially a square wave having
a predetermined amplitude,
the cycle indicator is arranged to indicate when a network cycle of the supplying voltage ends,
the first integrator is arranged to form, from the square wave, a ramp wave whose value is reset by the reset device at the
end of each network cycle in order to generate a sawtooth wave voltage signal, whereby information about the ending of each
network cycle is obtained from the cycle indicator,
the second integrator is arranged to generate, from the square wave, a ramp wave voltage signal whose value increases during
each network cycle until the restricting circuit stops the increase in the value of the ramp wave voltage signal when predetermined
conditions are fulfilled,
the adder is arranged to add up the sawtooth wave voltage signal of the first integrator and the ramp wave voltage signal
of the second integrator into a sum signal (UΣ), and
the trigger circuit is arranged to supply an ignition pulse to a gate of the semiconductor switch (Tch) via the isolation transformer when the sum signal (UΣ) exceeds a predetermined trigger level.
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