| US 7,456,496 B2 | ||
| Package design and method of manufacture for chip grid array | ||
| Tan Kim Hwee, Singapore (Singapore); Roman Perez, Singapore (Singapore); Kee Kwang Lau, Singapore (Singapore); Alex Chew, Singapore (Singapore); and Antonio Dimaano, Singapore (Singapore) | ||
| Assigned to Advanpack Solutions Pte Ltd, Singapore (Singapore) | ||
| Filed on May 12, 2005, as Appl. No. 11/128,014. | ||
| Application 11/128014 is a division of application No. 10/236337, filed on Sep. 06, 2002, granted, now 6,929,981. | ||
| Prior Publication US 2005/0205987 A1, Sep. 22, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 23/02 (2006.01); H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—691 [257/738; 257/E21.499; 257/E23.061] | 16 Claims |
| 1. A chip level semiconductor chip package comprising:
a molded encapsulant surrounding a semiconductor chip that utilizes interconnection pillars, wherein said encapsulant surrounds
the front and sides of said semiconductor chip and interconnection pillars and allows for contact to the pillar edge and backside
of the semiconductor chip; and
a chip grid array (CGA) of solder balls or bumps attached to said interconnection pillars that provide electrical connections
to each pillar.
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