| US 7,456,487 B2 | ||
| Semiconductor device | ||
| Tsuneo Ogura, Kanagawa (Japan); Masakazu Yamaguchi, Kanagawa (Japan); Tomoki Inoue, Tokyo (Japan); Hideaki Ninomiya, Kanagawa (Japan); and Koichi Sugiyama, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 28, 2004, as Appl. No. 10/974,810. | ||
| Claims priority of application No. 2004-159468 (JP), filed on May 28, 2004. | ||
| Prior Publication US 2005/0263852 A1, Dec. 01, 2005 | ||
| Int. Cl. H01L 29/739 (2006.01) | ||
| U.S. Cl. 257—565 [257/563; 257/564; 257/566; 257/587; 257/E29.201] | 6 Claims |

| 1. A semiconductor device, comprising:
a first base layer of a first conductivity type;
a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer;
trenches formed on each side of the second base layers, and formed to be deeper than the second base layers;
an emitter layer formed along the trench on a surface of the second base layers;
a collector layer of the second conductivity type, provided below a second surface of the first base layer opposite to the
first surface;
an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than
on a side surface of the trench;
a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating
film;
a space section provided between the second base layers adjacent to each other;
bottom semiconductor layers respectively provided below bottoms of the trenches, each bottom semiconductor layer covering
a whole of the bottom surface of the corresponding trench, the bottom semiconductor layers having the first conductivity type
higher in impurity concentration than the first base layer,
a width between the bottom semiconductor layers adjacent to each other being smaller than a width between the trenches adjacent
to each other so as to accumulate carriers in the first base layer.
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